Why do RMWs require flushing of write buffer in TSO?
I have been reading "A Primer on Memory Consistency and Cache Coherence" to understand more about how cache coherence is involved in atomic operations.I am a bit confused by the following statement...
View ArticleWhy does updating a struct array sequentially become 4x slower when threads...
I am benchmarking a parallelized array processing function in C++20. I noticed a weird performance degradation that defies standard algorithmic logic.I have an array of simple tracking counters. When a...
View ArticleWhat is the practical use of non-shareable domain barriers on ARM?
What is the point of non-shareable domain memory barriers on ARM, specifically the instructions:dmb nshlddmb nshstMost descriptions are confusing and seem pointless. dmb nshld is defined as:Operation...
View ArticleIs assembly implemented only in software?
I have a few confusionsIs assembly implemented only in software with assembler?Who updates and writes assemblers?Is the cpu not even aware that assembly exists?If let's say Intel releases a new cpu...
View ArticleWhat are practical uses of non-shareable domain barriers on Arm?
I'm trying to figure out exactly what the point of the non-shareable domain memory barriers are on Arm, referring specifically to the two following instructions:dmb nshlddmb nshstThe problem is that...
View ArticleComputer programs from the point of view of CPU
This might sound a bit naive, but, I'm unable to find an appropriate answer to the question in my mind.Let's say there is an algorithm X, which is implemented in 10 different programming languages....
View ArticleObserved cycle/iter greater than what's expected in simple x86 loop kernel
I am on a Skylake-X machine. Here's a very simple loop:%include "events_asm.inc"section .datafmt: db "CYCLES = %lu, RETIRED = %lu", 10, 0section .textglobal mainextern perf_measure2kernel: mov rax,...
View ArticleCan modern x86 CPUs do ideal out of order execution?
My mental model for out of order execution is to think of it as like a sliding window on the instruction stream, where if there are any instructions in the window that are ready (their inputs have...
View ArticleC programming and error_code variable efficiency
Most code I have ever read uses a int for standard error handling (return values from functions and such). But I am wondering if there is any benefit to be had from using a uint_8 will a compiler --...
View ArticleHow do I serialize a floating point number?
In the past I've written code to manually serialize a binary representation of a IEEE 754 number, however, it seems like several projects simply reinterpret a floating point number as a byte array and...
View ArticleExclusive Load/Store instructions fail with some MMU configurations on real...
I run into a strange issue (can't explain it myself) when using the exclusive load (ldaxr, ldxr, ...) and store (stxr, ...) instructions on real hardware (Raspberry Pi 3B+ -> Cortex A-53). These...
View ArticlePorting 32 bit C++ code to 64 bit - is it worth it? Why? [closed]
I am aware of some the obvious gains of the x64 architecture (higher addressable RAM addresses, etc)... but:What if my program has no real need to run in native 64 bit mode. Should I port it anyway?Are...
View ArticleExclusive load and store instructions require enabled caches on real hardware...
I run into a strange issue (can't explain it myself) when using the exclusive load (ldaxr, ldxr, ...) and store (stxr, ...) instructions on real hardware (Raspberry Pi 3B+ -> Cortex A-53). These...
View ArticleWhy is rep movsb slow for overlapping forward memmove, and why does libc use it?
TL;DR: memmove that uses rep movsb is magnitudes slow on overlapping array of 8193 bytes compared to memmove for 8191 elements that doesn't use rep movsb.I'm asking why.Consider the following...
View ArticleAre all programs eventually converted to assembly instructions? [closed]
From what I understand processor circuitry varies greatly from chip to chip and therefore may require different low level instructions to execute the same high level code. Are all programs eventually...
View ArticleWhy is xchg instruction with memory operand always atomic?
xchg with memory operand is always atomic, without the need of lock prefix. There's no way to make it non-atomic.Why such a decision was made?Is it useful decision, considering modern implementations...
View ArticleWhat is the difference between Node and Cell in NUMA system?
Can someone explain the difference between a Node and a Cell in a NUMA system? They seem to refer to the same thing.
View ArticleItanium seq_cst Fence and Relaxed Atomics Not Using Plain Loads and Stores
Something I always found strange about the C++ memory model was the fact that, up until C++20, using relaxed atomics and seq_cst fences wasn't equivalent to using seq_cst operations. I assumed this was...
View ArticleWhy didn't the x86-32 architecture get more general purpose registers before...
The x86-32 architecture does have 8 x 32bit general purpose registers. These are EAX, EBX, ECX, EDX, ESI, EDI, ESP and EBP.But why did it take until the x86-64 architecture for this number to double?If...
View ArticleIn C++ atomic operations, are the generated values allowed to circularly...
Very similar to In C++ atomic operations, are the generated values allowed to circularly depend on their own computations? but the example used is different (see below).As described in cppreference...
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